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universal ct0 subsystem integrated circuit fb suffix plastic package case 848b (qfp52) 52 1 device tested operating temperature range package ordering information mc13109afb t a = 20 to 85 c qfp52 MC13109AFTA lqfp48 fta suffix plastic package case 932 (lqfp48) 48 1 order this document by mc13109a/d 1 motorola rf/if device data
the mc13109a integrates several of the functions required for a cordless telephone into a single integrated circuit. this significantly reduces component count, board space requirements, and external adjustments. it is designed for use in both the handset and the base. ? dual conversion fm receiver complete dual conversion receiver antenna input to audio output 80 mhz maximum carrier frequency rssi output carrier detect output with programmable threshold comparator for data recovery operates with either a quad coil or ceramic discriminator ? compander expandor includes mute, digital volume control and speaker driver compressor includes mute, alc and limiter ? dual universal programmable pll supports new 25 channel u.s. standard with no external switches universal design for domestic and foreign ct0 standards digitally controlled via a serial interface port receive side includes 1st lo vco, phase detector, and 14bit programmable counter and 2nd lo with 12bit counter transmit section contains phase detector and 14bit counter mpu clock output eliminates need for mpu crystal ? supply voltage monitor externally adjustable trip point ? 2.0 to 5.5 v operation with onethird the power consumption of competing devices mute expander simplified block diagram 1st mixer data out rx in 2nd mixer carrier detect tx out tx in tx vco limiting if amplifier detector 2nd lo pll 1st lo pll rssi mute compressor tx phase detector m p serial interface low battery detect rx out spi low battery indicator this device contains 6,609 active transistors. ? motorola, inc. 1999 rev 1
mc13109a 2 motorola rf/if device data figure 1. mc13109afb test circuit c1 935pf c2 4.3pf xl1 10.24 mhz c44 10 m f c4 0.01 m f c3 0.047 m f r33 3.0k r34 1.5k c45 0.1 m f r35 32.4k c46 0.0047 m f r36 22.1k c43 0.1 m f r31 100k r32 100k v cc/2 ext_ref v cce rx_audio open c42 5.0nf r29 49.9k r30 49.9k c40 1.0 m f v cca c30 1.0 m f ext_c_in r27 49.9k c38 5.0nf r28 49.9k c47 1.0 m f tx_in l1 mix1_in c36 0.01 m f c35 0.01 m f open in out 1 2 3 c34 1.0 m f in out 1 2 3 gnd cf2 ext_if 455k in r23 10.2 r24 10 r23 1.5k c33 0.1 m f c32 0.1 m f c31 0.1 m f c30 0.1 m f c29 10 m f v cc l2 r22 12k c28 0.1 m f c27 0.1 m f r21 8.2k c26 0.01 m f det_out audio_in_in r20 49.9k c25 1.0 m f c24 510pf r19 49.9k pre_amp r18 20k r17 5.62k c22 0.1 m f c21 0.033 m f c23 0.001 m f da_fil da_in v cca c19 10 m f c20 0.1 m f e_out exp_if ext_sa_in c18 1.0 m f r16 49.9k c16 510 pf r14 130 sa_out r13 3.9k v ccd v cc r12 100k c15 10pf u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd clk_5.0v open v cce r11 1.0k clk_5.0v en_5.0v r10 1.0k r9 1.0k en_5.0v open open data_5.0v 5.0v 1 2 14 3 7 6 7 4 5 14 8 7 10 9 14 13 12 14 11 7 mps5179 q1 r6 1.0k c12 33pf c11 47pf c10 68pf r7 22.1k r5 22.1k c9 33pf l3 0.22 m h c8 18pf c7 15pf 1n5140 c6 0.022 m f r4 100k r2 32.4k c5 0.1 m f r3 32.4k r1 1.5k c48 1.0 m f v cca c14 1.0 m f r8 100k tx_vco ext 50 c17 47 m f lo 2 in lo 2 out pll v ref rx pd gnd pll tx pd e cap tx vco data en clk clk out cd out/ hardware interrupt bd out da out sa out sa in e out v cc audio da in pre amp out rx audio in det out rssi q coil v cc rf lim c2 lim c1 lim in gnd rf mix 2 out mix 2 in v b mix 1 out mix 1 in2 mix 1 in1 lo 1 in lo 1 out v cap ctrl gnd audio tx in amp out c in c cap lim out spl amp in tx out ref n/a n/a status out n/a 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 v b pll v ref low battery detect v b spkr mute carrier detect rssi 1st lo 2nd mix alc 13 12 11 10 9 8 7 6 5 4 3 2 1 toko a7mes12597z v cc 330 v b ref spkr amp vol ctrl expander e cap data amp v b pre amp 2nd lo 1st mix compressor limiter 2nd lo spl amp tx mute half supply reference 2nd lo 10.240 r phase detect x t phase detect x 14b prog r ctr x 1st lo 14b prog t ctr x p serial interface m prog clk ctr 2.2v voltage regulator bandgap reference detector if amp/ limiter 1st lo vco + + + + r15 49.9k c13 0.01 m f rx mute c41 0.47 m f mic_ amp out open lo1 12b prog ref ctr 1 4 25 cf1 10.7 mhz cf2 455 mhz data_5.0 v
mc13109a 3 motorola rf/if device data figure 2. MC13109AFTA test circuit c9 33pf c1 935pf c2 4.3pf xl1 10.24 mhz c44 10 m f c4 0.01 m f c3 0.047 m f r33 3.0k r34 1.5k c45 0.1 m f r35 32.4k c46 0.0047 m f r36 22.1k c43 0.1 m f r31 100k r32 100k v cc/2 ext_ref v cce rx_audio open c42 5.0nf r29 49.9k r30 49.9k c40 1.0 m f v cca c30 1.0 m f mic_ amp out r27 49.9k c38 5.0nf r28 49.9k c47 1.0 m f tx_in open lo1 l1 mix1_in c35 0.01 m f open in out 1 2 3 c34 1.0 m f in out 1 2 3 gnd cf2 ext_if 455k in r23 10.2 r24 10 r23 1.5k c33 0.1 m f c32 0.1 m f c31 0.1 m f c30 0.1 m f c29 10 m f v cc l2 r22 12k c28 0.1 m f c27 0.1 m f r21 8.2k det_out audio_in_in r20 49.9k c25 1.0 m f c24 510pf r19 49.9k pre_amp r18 20k r17 5.62k c22 0.1 m f c21 0.033 m f c23 0.001 m f da_fil da_in v cca e_out exp_if ext_sa_in c18 1.0 m f r16 49.9k c16 510pf r14 130 sa_out r13 3.9k v ccd v cc r12 100k c15 10pf u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd u1 da db v cc ls09 out gnd open v cce r11 1.0k clk_5.0v en_5.0v r9 1.0k en_5.0v open data_5.0v 5.0v 1 2 14 3 7 6 7 4 5 14 8 7 10 9 14 13 12 14 11 7 mps5179 q1 r6 1.0k c12 33pf c11 47pf c10 68pf r7 22.1k r5 22.1k l3 0.22 m h c8 18pf c7 15pf 1n5140 c6 0.022 m f r4 100k r2 32.4k c5 0.1 m f r3 32.4k r1 1.5k c48 1.0 m f v cca tx_vco ext 50 c17 47 m f lo2 in lo2 out pll v ref rx pd gnd pll tx pd e cap tx vco data en clk clk out cd out/ hardware interrupt bd out da out sa out sa in e out v cc audio da in pre amp out rx audio in det out rssi q coil v cc rf lim c2 lim c1 lim in gnd rf mix 2 out mix 2 in v b mix 1 out mix 1 in 2 mix 1 in 1 lo1 in lo1 out v cap ctrl gnd audio tx in amp out c in c cap lim out spl amp in tx out ref 12b prog ref ctr v b pll v ref low battery detect v b spkr mute carrier detect rssi 1st lo 2nd mix v b alc 48 47 46 45 44 43 42 41 40 38 37 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v cc toko a7mes12597z v cc 330 39 35 36 c13 0.01 m f c14 1.0 m f r8 100k r10 1.0k r15 49.9k c19 10 m f c20 0.1 m f c26 0.01 m f c36 0.01 m f c41 0.47 m f spl amp tx mute limiter compressor half supply reference 2nd lo 1st mix pre amp rx mute data amp v b vol ctrl spkr amp ref 2nd lo 1st lo expander e cap detector bandgap 2.2v 14b prog p serial prog t phase 2nd lo + 1st lo if amp/ + + + clk ctr interface t ctr m x voltage regulator reference 14b prog r ctr x detect x r phase detect x 10.240 limiter vco 1 4 25 open data_ 5.0 v clk_5.0 v ext_c_in cf1 10.7 mhz cf2 455 mhz
mc13109a 4 motorola rf/if device data maximum ratings rating symbol value unit power supply voltage v cc 0.5 to + 5.5 vdc junction temperature t j 65 to +150 c notes: 1. devices should not be operated at or outside these limits. the arecommended operating conditionso table provides for actual device operation. 2. esd data available upon request. 3. meets human body model (hbm) 2000v and machine model (mm) 200v. recommended operating conditions characteristic min typ max unit v cc 2.0 5.5 vdc operating ambient temperature 20 85 c note : all limits are not necessarily functional concurrently. electrical characteristics (v cc = 2.6 v, t a = 25 c, rf in = 46.61 mhz, f dev = 3.0 khz, f mod = 1.0 khz; test circuit figure 1.) characteristic min typ max unit power supply static current active mode (v cc = 2.6 v) 6.1 12 ma active mode (v cc = 3.6 v) 6.5 ma receive mode (v cc = 2.6 v) 3.9 7.0 ma receive mode (v cc = 3.6 v) 4.3 ma standby mode (v cc = 2.6 v) 320 600 m a standby mode (v cc = 3.6 v) 550 m a inactive mode (v cc = 2.6 v) 40 80 m a inactive mode (v cc = 3.6 v) 54 m a
mc13109a 5 motorola rf/if device data electrical characteristics (continued) fm receiver the fm receivers can be used with either a quad coil or a ceramic resonator. the fm receiver and 1st lo have been designed to work for all country channels, including 25 channel u.s., without the need for any external switching circuitry (see figure 25.) (test conditions: v cc = 2.6 v, t a = 25 c, f o = 46.61 mhz, f dev = 3.0 khz, f mod = 1.0 khz.) characteristic condition input pin measure pin symbol min typ max unit sensitivity (input for 12 db sinad) matched impedance differential input mix 1 in 1/2 det out v sin 0.7 m vrms 1st mixer voltage conversion gain v in = 1.0 mvrms, with cf 1 as load mix 1 in 1/2 mix 1 out mx gain1 10 db 2nd mixer voltage conversion gain v in = 3.0 mvrms, with cf 2 as load mix 2 in mix 2 out mx gain2 20 db 1st mixer input impedance mix 1 in 1 mix 1 in 2 r p1 c p1 0.88 2.5 k w pf 2nd mixer input impedance mix 2 in r p2 c p2 3.0 2.7 k w pf 1st mixer output impedance mix 1 out r p1 out c p1 out 390 1.8 w pf 2nd mixer output impedance mix 2 out r p2 out c p2 out 1.5 12 k w pf 1st and 2nd mixer voltage gain total v in = 1.0 mvrms, with cf 1 and cf 2 as load mix 1 in 1/2 mix 2 out mx gain t 24 27 db if 3.0 db limiting sensitivity f in = 455 khz lim in det out if sens 55 100 m vrms total harmonic distortion (ccitt filter) with r c = 8.2 k w / 0.01 m f filter at det out mix 1 in 1/2 det out thd 1.0 3.0 % recovered audio with r c = 8.2 k w / 0.01 m f filter at det out mix 1 in 1/2 det out afo 80 100 154 mvrms demodulator bandwidth lim in det out bw 20 khz signal to noise ratio v in = 10 mvrms, r c = 8.2 k w /0.01 m f mix 1 in 1/2 det out sn 50 db am rejection ratio 30% am, v in = 10 mvrms, r c = 8.2 k w /0.001 m f mix 1 in 1/2 det out amr 30 40 db first mixer 3rd order intercept (input referred) matched impedance input mix 1 in 1/2 mix 1 out toi mix1 10 dbm second mixer 3rd order intercept (input referred) matched impedance input mix 2 in mix 2 out toi mix2 27 dbm detector output impedance det out z o 870 w
mc13109a 6 motorola rf/if device data electrical characteristics (continued) rssi/carrier detect connect 0.01 m f to gnd from arssio output pin to form the carrier detect filter. acd outo is an open collector output which requires an external 100 k w pullup resistor to v cc . the carrier detect threshold is programmable through the mpu interface. (r l = 100 k w , v cc = 2.6 v, t a = 25 c.) characteristic condition input pin measure pin symbol min typ max unit rssi output current dynamic range mix 1 in rssi rssi 65 db carrier sense threshold cd threshold adjust = (10100) mix 1 in cd out v t 11 mvrms hysteresis mix1 in cd out hys 1.5 db output high voltage v in = 0 m vrms, r l = 100 k w , cd = (10100) mix 1 in cd out v oh 2.6 v output low voltage v in = 100 m vrms, r l = 100 k w , cd = (10100) mix 1 in cd out v ol 0.01 0.4 v carrier sense threshold adjustment range programmable through mpu interface v trange 20 11 db carrier sense threshold number of steps programmable through mpu interface v tn 32 data amp comparator inverting hysteresis comparator. open collector output with internal 100 k w pullup resistor. a band pass filter is connected between the adet outo pin and the ada ino pin with component values as shown in the attached block diagram. the ada ino input signal is ac coupled. (v cc = 2.6 v, t a = 25 c) characteristic condition input pin measure pin symbol min typ max unit hysteresis da in da out hys 30 40 50 mv threshold voltage da in da out v t v cc 0.9 v cc 0.7 v cc 0.5 v input impedance da in z i 12 k w output impedance da out z o 104 k w output high voltage v in = v cc 1.0 v, i oh = 0 ma da in da out v oh v cc 0.1 2.6 v output low voltage v in = v cc 0.4 v, i ol = 0 ma da in da out v ol 0.04 0.4 v
mc13109a 7 motorola rf/if device data electrical characteristics (continued) preamplifier/expander/rx mute/volume control the preamplifier is an inverting railtorail output swing operational amplifier with the noninverting input terminal connected to the internal v b half supply reference. external resistors and capacitors can be connected to set the gain and frequency response. the expander analog ground is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. the volume control can be adjusted through the mpu interface. the arx audio ino input signal is ac coupled. (test conditions: v cc = 2.6 v, t a = 25 c, f in = 1.0 khz, set external preamplifier r's for gain of 1, volume control = (0111).) characteristic condition input pin measure pin symbol min typ max unit preamp open loop gain rx audio in preamp a vol 60 db preamp gain bandwidth rx audio in preamp gbw 100 khz preamp maximum output swing r l = 10 k w rx audio in preamp v omax v cc 0.3 vpp expander 0 db gain level v in = 10 dbv rx audio in e out g 3.0 0.3 3.0 db expander gain tracking v in = 20 dbv, output relative to g rx audio in e out g t 21 19.84 19 db v in = 30 dbv, output relative to g 42 40.12 37 total harmonic distortion v in = 10 dbv rx audio in e out thd 0.2 % maximum output voltage increase input voltage until output voltage thd = 5%, then measure output voltage. r l = 10 k w rx audio in e out v omax 5.0 dbv attack time e cap = 1.0 m f, r filt = 20 k w (see appendix b) rx audio in e out t a 3.0 ms release time e cap = 1.0 m f, r filt = 20 k w (see appendix b) rx audio in e out t r 13.5 ms compressor to expander crosstalk v (rx audio in) = 0 vrms, v in = 10 dbv c in e out c t 76 db rx mute v in = 10 dbv no popping detectable during rx mute transitions rx audio in e out m e 65 db volume control range programmable through mpu interface v crange 14 16 db volume control steps programmable through mpu interface v cn 16
mc13109a 8 motorola rf/if device data electrical characteristics (continued) speaker amplifier/sp mute the speaker amplifier is an inverting railtorail operational amplifier. the noninverting input terminal is connected to the internal v b half supply reference. external resistors and capacitors are used to set the gain and frequency response. the asa ino input is ac coupled. (test conditions: v cc = 2.6 v, t a = 25 c, f in = 1.0 khz, external resistors set for gain of 1.) characteristic condition input pin measure pin symbol min typ max unit maximum output swing v cc = 2.3 v, r l = 130 w sa in sa out v omax 0.8 v pp l v cc = 2.3 v, r l = 600 w v34v 2.0 30 v cc = 3.4 v, r l = 600 w 3.0 sp mute v in = 20 dbv r l = 130 w no popping detectable during sp mute transitions sa in sa out m sp 67 db mic amplifier the mic amplifier is an inverting railtorail output operational amplifier with the noninverting input terminal connected to the internal v b half supply reference. external resistors and capacitors are connected to set the gain and frequency response. the atx ino input is ac coupled. (test conditions: v cc = 2.6 v, t a = 25 c, f in = 1.0 khz, external resistors set for gain of 1.) characteristic condition input pin measure pin symbol min typ max unit open loop gain tx in amp out a vol 60 db gain bandwidth tx in amp out g bw 100 khz maximum output swing r l = 10 k w tx in amp out v omax v cc 0.3 vpp
mc13109a 9 motorola rf/if device data electrical characteristics (continued) compressor/alc/tx mute/limiter the compressor analog gound is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. the ac ino input is ac coupled. the alc (automatic level control) provides a soft limit to the output signal swing as the input voltage increases slowly (i.e., a sine wave is maintained). the limiter circuit limits rapidly changing signal levels by clipping the signal peaks. the alc and/or limiter can be disabled through the mpu serial interface. (test conditions: v cc = 2.6 v, f in = 1.0 khz, t a = 25 c.) characteristic condition input pin measure pin symbol min typ max unit compressor 0 db gain level v in = 10 dbv, alc disabled, limiter disabled c in lim out g 3.0 0.06 3.0 db compressor gain tracking v in = 30 dbv, output relative to g c in lim out g t 11 10.12 9.0 db v in = 50 dbv, output relative to g 23 20.16 17 maximum compressor gain v in 70 dbv c in lim out a vmax 29 db total harmonic distortion v in 10 dbv, alc disabled, limiter disabled c in lim out thd 0.5 % input impedance c in lim out z in 16 k w attack time c cap = 1.0 m f, r filt = 20 k w (see appendix b) c in lim out t a 3.0 ms release time c cap = 1.0 m f, r filt = 20 k w (see appendix b) c in lim out t r 13.5 ms expander to compressor crosstalk v (c in) = 0 vrms, v in = 10 dbv rx audio in lim out c t 43.6 db tx data mute v in = 10 dbv, alc disabled no popping detectable during rx mute transitions c in lim out m e 76 db alc dynamic range c in lim out dr 18 to 2.5 dbv alc output level v in = 18 dbv c in lim out alc out 16 dbv v in = 2.5 dbv 11.4 limiter output level alc disabled c in tx out v lim 0.8 v pp
mc13109a 10 motorola rf/if device data electrical characteristics (continued) splatter amplifier the splatter amplifier is an inverting railtorail output operational amplifier with the noninverting input terminal connected to the internal v b half supply reference. external resistors and capacitors can be connected to set the gain and frequency response. the aspl amp ino input is ac coupled. (test conditions: v cc = 2.6 v, t a = 25 c, f in = 1.0 khz, external resistors set for gain of 1.) characteristic condition input pin measure pin symbol min typ max unit open loop gain spl amp in tx out a vol 60 db gain bandwidth spl amp in tx out gbw 100 khz maximum output swing r l = 10 k w spl amp in tx out v omax v cc 0.3 v pp tx audio path recommendation the recommended configuration for the tx audio path includes setting the microphone amplifier gain to 16 db using the external gain setting resistors and setting the splatter amplifier gain to 9.0 db using the external gain setting resistors. pll voltage regulator the pll supply voltage is regulated to a nominal of 2.2 v. the av cc audioo pin is the supply voltage for the internal voltage regulator. the apll v ref o pin is the 2.2 v regulated output voltage. two capacitors with 10 m f and 0.01 m f values must be connected to the apll v ref o pin to filter and stabilize this regulated voltage. the voltage regulator provides power for the 2nd lo, rx and tx pll's, and mpu interface. the voltage regulator can also be used to provide a regulated supply voltage for external ic's. rx and tx pll loop performance are independent of the power supply voltage when the voltage regulator is used. the voltage regulator requires about 200 mv of aheadroomo. when the power supply decreases to within about 200 mv of the output voltage, the regulator will go out of regulation but the output voltage will not turn off. instead, the output voltage will maintain about a 200 mv delta to the power supply voltage as the power supply voltage continues to decrease. the apll v ref o pin can be connected to av cc audioo by the external wiring if voltage higher than 2.2 v is required. but it should not be connected to other supply except av cc audioo. the voltage regulator is aono in the active and rx modes. in the standby and inactive modes, the voltage regulator is turned off to reduce current drain and the apll v ref o pin is internally connected to av cc audioo (i.e., the supply voltage is maintained but is now unregulated). (test conditions: v cc = 2.6 v, t a = 25 c.) characteristic condition input pin measure pin symbol min typ max unit output voltge level v cc = 2.6 v, o l = 0 ma v cc pll v out 2.2 v line regulation i l = 0 ma, v cc = 2.6 to 5.5 v v cc v cc pll reg line 3.66 40 mv load regulation v cc = 2.6 v, i l = 0 to 1.0 ma v cc v cc pll reg load 40 2.28 mv
mc13109a 11 motorola rf/if device data electrical characteristics (continued) low battery detect an external resistor divider is connected to the arefo input pin to set the threshold for the low battery detect. the voltage at the arefo input pin is compared to an internal 1.23 v bandgap reference voltage. the abd outo pin is open collector and requires and external pullup resistor to v cc . (test conditions: v cc = 2.6 v, t a = 25 c.) characteristic condition input pin measure pin symbol min typ max unit average threshold voltage take average of rising and falling threshold ref ref/ bd out threshold 1.23 v hysteresis ref ref/ bd out hys 2.0 mv input current v in = 1.6 v ref i in 12.33 50 na output high voltage v ref = 1.6, r l = 3.9 k w ref bd out v oh v cc 0.1 2.59 v output low voltage v ref = 0.9, r l = 3.9 k w ref bd out v ol 0.6 0.4 v figure 3. data amp operation data signal data amp data amp output hysteresis
mc13109a 12 motorola rf/if device data pin function description 48tqfp pin 52qfp pin symbol type description 1 2 1 2 lo 2 in lo2 out these pins form the pll reference oscillator when connected to an external parallelresonant crystal (10.24 mhz typical). the reference oscillator is also the second local oscillator (lo 2 ) for the rf receiver. 3 3 pll v ref supply voltage regulator output pin. the internal voltage regulator provides a stable power supply voltage for the rx and tx pll's and can also be used as a regulated supply voltage for the other ic's. 4 4 rx pd output three state voltage output of the rx phase detector. this pin is either ahigho, alowo, or ahigh impedanceo depending on the phase difference of the phase detector input signals. during lock, very narrow pulses with a frequency equal to the reference frequency are present. this pin drives the external rx pll loop filter. it is important to minimize the line length and capacitance of this pin. 5 5 gnd pll gnd ground pin for pll section of ic. 6 6 tx pd output three state voltage output of the tx phase detector. this pin is either ahigho, alowo, or ahigh impedanceo depending on the phase difference of the phase detector input signals. during lock, very narrow pulses with a frequency equal to the reference frequency are present. this pin drives the external tx pll loop filter. it is important to minimize the line length and capacitance on this pin. 7 7 e cap expander rectifier filter capacitor pin. connect capacitor to v cc . 8 8 tx vco input transmit divide counter input which is driven by an ac coupled external transmit loop vco. the minimum signal level is 200 mv pp @ 80.0 mhz. this pin also functions as the test mode input for the counter tests. 9 10 11 9 10 11 data en clk input microprocessor serial interface input pins for programming various counters and control functions. 12 12 clk out output microprocessor clock output which is derived from the 2nd lo crystal oscillator and a programmable divider. it can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. the driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the pcb. this output also functions as the output for the counter test modes. n/a 14 status out output this pin indicates when the internal latches may have lost memory due to a power glitch. 13 15 cd out/ hardware interrupt output/ input dual function pin; 1) carrier detect output (open collector with external 100 k w pullup resistor. 2) hardware interrupt input which can be used to awakeupo from inactive mode. 14 16 bd out output low battery detect output (open collector with external pullup resistor). 15 17 da out output data amplifier output (open collector with internal 100 k w pullup resistor). 16 18 sa out output speaker amplifier output. 17 19 sa in input speaker amplifier input (ac coupled). 18 20 e out output expander output. 19 21 v cc audio supply v cc supply for audio section. 20 22 da in input data amplifier input (ac coupled). 21 23 preamp out output preamplifier output for connection of preamplifier feedback resistor. 22 24 rx audio in input rx audio input to preamplifier (ac coupled). 23 25 det out output audio output from fm detector. 24 26 rssi receive signal strength indicator filter capacitor. n/a 27 n/a not used. 25 28 q coil a quad coil or ceramic discriminator are connected to this pin. 26 29 v cc rf supply v cc supply for rf receiver section. 27 28 30 31 lim c2 lim c1 if amplifier/limiter capacitor pins.
mc13109a 13 motorola rf/if device data pin function description (continued) 48tqfp pin 52qfp pin symbol type description 29 32 lim in input signal input for if amplifier/limiter. 30 33 gnd rf gnd ground pin for rf section of the ic. 31 34 mix 2 out output second mixer output. 32 35 mix 2 in input second mixer input. 33 36 v b internal half supply analog ground reference. 34 37 mix 1 out output first mixer output. 35 38 mix 1 in 2 input negative polarity first mixer input. 36 39 mix 1 in 1 input positive polarity first mixer input. 37 38 40 41 lo 1 in lo 1 out tank elements for 1st lo multivibrator oscillator are connected to these pins. 39 42 v cap ctrl 1st lo varactor control pin. 40 43 gnd audio gnd ground for audio section of the ic. 41 44 tx in input tx path input to microphone amplifier (ac coupled). 42 45 amp out output microphone amplifier output. 43 46 c in input compressor input (ac coupled). 44 47 c cap compressor rectifier filter capacitor pin. connect capacitor to v cc . 45 48 lim out output tx path limiter output. 46 49 spl amp in input splatter amplifier input (ac coupled). 47 50 tx out output tx path audio output. 48 51 ref input reference voltage input for low battery detect. n/a 52 n/a not used. power supply voltage this circuit is used in a cordless telephone handset and base unit. the handset is battery powered and can operate on two or three nicad cells or on 5.0 v power. pll frequency synthesizer general description figure 4 shows a simplified block diagram of the programmable universal dual phase locked loop (pll). this dual pll is fully programmable through the mcu serial interface and supports most country channel frequencies including usa (25 ch), france, spain, australia, korea, new zealand, u.k., netherlands and china (see channel frequency tables in appendix a). the 2nd local oscillator and reference divider provide the reference frequency for the rx and tx pll loops. the programmed divider value for the reference divider is selected based on the crystal frequency and the desired rx and tx reference frequency values. additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 khz and 6.25 khz reference frequencies required for the u.k. the 14bit tx counter is programmed for the desired transmit channel frequency. the 14bit rx counter is programmed for the desired first local oscillator frequency. all counters power up in the proper default state for usa channel #6 and for a 10.24 mhz reference frequency crystal. internal fixed capacitors can be connected to the tank circuit of the 1st lo through microprocessor control to extend the sensitivity of the 1st lo for u.s. 25 channel operation.
mc13109a 14 motorola rf/if device data 14b programmable rx counter figure 4. dual pll simplified block diagram 14b programmable tx counter 12b programmable reference counter 25 1 4 lo 2 in lo 2 out 1, 1 2, 2 tx pd 8, 8 6, 6 tx vco rx pd 4, 4 lo 1 in 37, 40 lo 1 out 38, 41 tx phase detector rx phase detector tx vco lpf tx ref rx ref u.k. base u.k. handset u.k. handset u.k. base lpf v cap ctrl 39, 42 1st lo lo 2 electrical characteristics (v cc = 2.6 v, t a = 25 c) characteristic condition measure pin symbol min typ max unit pll pin dc input voltage low data clk en hardware int. v il 0.3 v input voltage high data clk en v ih apll v ref o 0.3 av cc audioo v input current low v in = 0.3 v data clk en i il 5.0 3.0 m a input current high v in = (v cc audio) 0.3 data clk en i ih 0.6 5.0 m a hysteresis voltage data clk en v hys 1.0 v output current high rx pd tx pd i oh 0.7 ma output current low rx pd tx pd i ol 0.7 ma output voltage low i il = 0.7 ma rx pd tx pd v ol (pll v ref )* 0.2 v output voltage high i ih = 0. 7ma rx pd tx pd v oh (pll v ref )* 0.8 v tristate leakage current v = 1.2 v rx pd tx pd i oz 50 50 na input capacitance data clk en c in 8.0 pf output capacitance rx pd tx pd c out 8.0 pf
mc13109a 15 motorola rf/if device data electrical characteristics (continued) (v cc = 2.6 v, t a = 25 c) characteristic unit max typ min symbol measure pin condition pll pin interface en to clk setup time en, clk t suec 200 ns data to clk setup time data, clk t sudc 100 ns hold time data, clk t h 90 ns recovery time en, clk t rec 90 ns input pulse width en, clk t w 100 ns input rise and fall time data clk en t r , t f 9.0 m s mpu interface powerup delay 90% of pll v ref to data, clk, en t pumpu 100 m s pll loop 2nd lo frequency lo 2 in lo 2 out f lo 12 mhz atx vcoo input frequency v in = 200 mv pp tx vco f txmax 80 mhz pll i/o pin specifications the 2nd lo, rx and tx pll's and mpu serial interface are normally powered by the internal voltage regulator at the apll v ref o pin. the apll v ref o pin is the output of a voltage regulator which is powered from the av cc audioo power supply pin. therefore, the maximum input and output levels for most pll i/o pins (lo 2 in, lo 2 out, rx pd, tx pd, tx vco) is the regulated voltage at the apll v ref o pin. the esd protection diodes on these pins are also connected to apll v ref o. internal level shift buffers are provided for the pins (data, clk, en, clk out) which connect directly to the microprocessor. the maximum input and output levels for these pins is v cc . figure 5 shows a simplified schematic of the pll i/o pins. figure 5. pll i/o pin simplified schematics pll v ref (2.2 v) in i/o v cc audio (2.0 to 5.5 v) pll v ref (2.2 v) v cc audio (2.0 to 5.5 v) clk out pin data, clk, and en pins lo 2 in, lo 2 out, rx pd, tx pd and tx vco pins out 2.0 m a 1.0 k w microprocessor serial interface the adatao, aclko, and aeno pins provide an mpu serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. the adatao and aclko pins are used to load data into the shift register. figure 6 shows adatao and aclko pin timing. data is clocked on positive clock transitions. figure 6. data and clock timing requirement data, clk, en data clk t sudc t r t f 50% 50% t h 10% 90% after data is loaded into the shift register, the data is latched into the appropriate latch register using the aeno pin. this is done in two steps. first, an 8bit address is loaded into the shift register and latched into the 8bit address latch register. then, up to 16bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. figure 7 shows the timing required on the en pin. latching occurs on the negative en transition.
mc13109a 16 motorola rf/if device data figure 7. enable timing requirement clk en t suec 50% 50% 50% t rec previous data latch last clock first clock 50% the state of the en pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. figure 8 shows the address and data programming diagrams. in the data programming mode, there must not be any clock transitions when aeno is high. the clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the aeno high state. the convention in these figures is that latch bits to the left are loaded into the shift register first. figure 8. microprocessor interface programming mode diagrams data 8bit address en data en address register programming mode 16bit data data register programming mode latch latch msb msb lsb lsb the mpu serial interface is fully operational within 100 m s after the power supply has reached its minimum level during powerup (see figure 9). the mpu interface shift registers and data latches are operational in all four power saving modes; inactive, standby, rx, and active modes. data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. figure 9. microprocessor serial interface powerup delay v cc t pumpu 2.0 v data, clk, en status out this is a digital output which indicates whether the latch registers have been reset to their powerup default values. latch powerup default values are given in figure 28. if there is a power glitch or esd event which causes the latch registers to be reset to their default values, the astatus outo pin will indicate this to the mpu so it can reload the correct information into the latch registers. figure 10. status out operation status latch register bits status out logic level latch bits not at powerup default value 0 latch bits at powerup default value 1 data registers figure 11 shows the data latch registers and addresses which are used to select each of these registers. latch bits to the left (msb) are loaded into the shift register first. the lsb bit must always be the last bit loaded into the shift register. adon't careo bits can be loaded into the shift register first if 8bit bytes of data are loaded.
mc13109a 17 motorola rf/if device data 1. (00000001) latch address u.k. handset select 2. (00000010) 3. (00000011) 4. (00000100) 5. (00000101) 7. (00000111) 14bit tx counter msb lsb msb lsb msb lsb msb lsb msb lsb 14bit rx counter 12bit reference counter 5bit cd threshold control 4bit test mode 3bit 1st lo capacitor selection 14bit volume control u.k. base select alc disable not used limiter disable clk disable mpu clk1 mpu clk0 stdby mode rx mode tx mute rx mute sp mute tx counter latch rx counter latch reference counter latch mode control latch threshold control latch 7bit auxillary latch 6. (00000110) figure 11. microprocessor interface data latch registers reference frequency selection the alo 2 ino and alo 2 outo pins form a reference oscillator when connected to an external parallelresonant crystal. the reference oscillator is also the second local oscillator for the rf receiver. figure 12 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. figure 12. reference frequency and reference divider values reference u.k. base/ crystal divider handset reference frequency value divider frequency 10.24 mhz 2048 1 5.0 khz 10.24 mhz 1024 4 2.5 khz 11.15 mhz 2230 1 5.0 khz 12.00 mhz 2400 1 5.0 khz 11.15 mhz 1784 1 6.25 khz 11.15 mhz 446 4 6.25 khz 11.15 mhz 446 25 1.0 khz reference counter figure 13 shows how the reference frequencies for the rx and tx loops are generated. all countries except u.k. require that the tx and rx reference frequencies be identical. in this case, set au.k. base selecto and au.k. handset selecto bits to a0o. then the fixed divider is set to a1o and the tx and rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. the u.k. is a special case which requires a different reference frequency value of tx and rx. for u.k. base operation, set au.k. base selecto to a1o. for u.k. handset operation, set au.k. handset selecto to a1o. the netherlands is also a special case since a 2.5 khz reference frequency is used for both the tx and rx reference and the total divider value required is 4096 which is larger than the maximum divide value available from the 12bit reference divider (4095). in this case, set au.k. base selecto to a1o and set au.k. handset selecto to a1o. this will give a fixed divide by 4 for both the tx and rx reference. then set the reference divider to 1024 to get a total divider of 4096. mode control register power saving modes, mutes, disables, volume control, and microprocessor clock output frequency are all set by the control register. operation of the control register is explained in figures 14 through 21.
mc13109a 18 motorola rf/if device data 0 0 1 1 0 1 0 1 1 25 4 4 1 4 25 4 lo 2 out tx reference frequency figure 13. reference register programming mode 12b programmable reference counter 25 1 4 lo 2 in rx reference frequency u.k. base u.k. handset u.k. handset u.k. base u.k. handset select u.k. base select lo 2 tx divider value rx divider value application all but u.k. and netherlands u.k. baseset u.k. handset netherlands base and handset u.k. handset select msb lsb 12bit reference counter u.k. base select 14bit reference counter latch figure 14. control register bits msb lsb 4bit volume control alc disable not used limiter disable clk disable mpu clk1 mpu clk0 stdby mode rx mode tx mute rx mute sp mute figure 15. mute and disable control bit descriptions alc disable 1 0 automatic level control disabled normal operation limiter disable 1 0 limiter disabled normal operation clock disable 1 0 mpu clock output disabled normal operation tx mute 1 0 transmit channel muted normal operation rx mute 1 0 receive channel muted normal operation sp mute 1 0 speaker amp muted normal operation power saving operating modes when the mc13109a is used in a handset, it is important to conserve power in order to prolong battery life. there are five modes of operation; active, rx, standby, interrupt and inactive. in active mode, all circuit blocks are powered. in rx mode, all circuitry is powered down except for those circuit sections needed to receive a transmission from the base. in the standby and interrupt modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. in inactive mode, all circuitry is powered down except the mpu interface. latch memory is maintained in all modes. figure 16 shows the control register bit values for selection of each power saving mode and figure 17 show the circuit blocks which are powered in each of these operating mode. figure 16. power saving mode selection stdby mode bit rx mode bit acd out/hardware interrupto pin power saving mode 0 0 x active 0 1 x rx 1 0 x standby 1 1 1 or high impedance inactive 1 1 0 inactive
mc13109a 19 motorola rf/if device data figure 17. circuit blocks powered during power saving modes circuit blocks active rx standby inactive apll v ref o regulated voltage x x x 1 x 1 mpu interface x x x x 2nd lo oscillator x x x mpu clock output x x x rf receiver x x 1st lo vco x x rx pll x x carrier detect x x data amp x x low battery detect x x tx pll x rx audio path x tx audio path x note: 1. in standby and inactive modes, apll v ref o remains powered but is not regulated. it will fluctuate with v cc . inactive mode operation and hardware interrupt in some handset applications it may be desirable to power down all circuitry including the microprocessor (mpu). first put the mc13109a into the inactive mode, which turns off the mpu clock output (see figure 18), and then disable the microprocessor. in order to give the mpu adequate time to power down, the mpu clock output remains active for a minimum of one reference counter cycle (about 200 m s) after the command is given to switch into the ainactiveo mode. an external timing circuit should be used to initiate the turnon sequence. the acd outo pin has a dual function. in the active and rx modes it performs the carrier detect function. in the standby and inactive modes the carrier detect circuit is disabled and the acd outo pin is in a ahigho state due to the external pullup resistor. in the inactive mode the acd outo pin is the input for the hardware interrupt function. when the acd outo pin is pulled alowo by the external timing circuit, the mc13109a switches from the inactive to the interrupt mode thereby turning on the mpu clock output. the mpu can then resume control of the combo ic. the acd outo pin must remain low until the mpu changes the operating mode from interrupt to standby, active or rx modes. figure 18. hardware interrupt operation mode en cd out/hardware interrupt mpu clock out cd out low delay after mpu selects inactive mode to when cd turns off cd turns off external timer pulls pin low mpu initiates mode change timer output disabled mpu initiates inactive mode ampu clock outo remains active for a minimum of one count of reference counter after acd out/hardware interrupto pin goes high active/rx inactive interrupt standby/rx/active
mc13109a 20 motorola rf/if device data aclk outo divider programming the aclk outo pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. figure 19 shows the relationship between the crystal frequency and the clock output for different divider values. figure 20 shows the aclk outo register bit values. figure 19. clock output values crystal clock output divider crystal frequency 2 3 5 10 10.24 mhz 5.120 mhz 3.413 mhz 2.048 mhz 1.024 mhz 11.15 mhz 5.575 mhz 3.717 mhz 2.230 mhz 1.115 mhz 12.00 mhz 6.000 mhz 4.000 mhz 2.400 mhz 1.200 mhz figure 20. clock output divider clk out bit #1 clk out bit #2 clk out divider value 0 0 2 0 1 3 1 0 5 1 1 10 mpu aclk outo powerup default divider value the powerup default divider value is adivide by 10o. this provides an mpu clock of about 1.0 mhz after initial powerup. the reason for choosing this relatively low clock frequency after intial powerup is that some microprocessors that operate down to a 2.0 v power supply have a maximum clock frequency of 1.0 mhz. after initial powerup, the mpu can change the clock divider value to set the clock to the desired operating frequency. special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is asmootho (i.e., there will be no narrow clock pulses to disturb the mpu). mpu aclk outo radiated noise on circuit board the clock line running between the mc13109a and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. in order to minimize radiated noise, a 1.0 k w resistor is included onchip inseries with the aclk outo output driver. a small capacitor can be connected to the aclk outo line on the pcb to form a single pole low pass filter. this filter will significantly reduce noise radiated from the aclk outo line. volume control the volume control can be programmed in 2.0 db gain steps from 14 db to 16 db. the powerup default value is 0 db. figure 21. volume control volume control bit #3 volume control bit #2 volume control bit #1 volume control bit #0 volume control # gain/attenuation amount 0 0 0 0 0 14 db 0 0 0 1 1 12 db 0 0 1 0 2 10 db 0 0 1 1 3 8.0 db 0 1 0 0 4 6.0 db 0 1 0 1 5 4.0 db 0 1 1 0 6 2.0 db 0 1 1 1 7 0 db 1 0 0 0 8 2.0 db 1 0 0 1 9 4.0 db 1 0 1 0 10 6.0 db 1 0 1 1 11 8.0 db 1 1 0 0 12 10 db 1 1 0 1 13 12 db 1 1 1 0 14 14 db 1 1 1 1 15 16 db gain control register the gain control register contains bits which control the carrier detect threshold. operation of these latch bits are explained in figures 22 and 23. msb lsb 5bit cd threshold control figure 22. gain control latch bits
mc13109a 21 motorola rf/if device data carrier detect threshold programming the acd outo pin will give an indication to the microprocessor if a carrier signal is present on the selected channel. the nominal value and tolerance of the carrier detect threshold is given in the carrier detect specification section of this document. if a different carrier detect threshold value is desired, it can be set through the mpu interface as shown in figure 23 below. figure 23. carrier detect threshold control cd bit #4 cd bit #3 cd bit #2 cd bit #1 cd bit #0 cd control # carrier detect threshold 0 0 0 0 0 0 20 db 0 0 0 0 1 1 19 db 0 0 0 1 0 2 18 db 0 0 0 1 1 3 17 db 0 0 1 0 0 4 16 db 0 0 1 0 1 5 15 db 0 0 1 1 0 6 14 db 0 0 1 1 1 7 13 db 0 1 0 0 0 8 12 db 0 1 0 0 1 9 11 db 0 1 0 1 0 10 10 db 0 1 0 1 1 11 9.0 db 0 1 1 0 0 12 8.0 db 0 1 1 0 1 13 7.0 db 0 1 1 1 0 14 6.0 db 0 1 1 1 1 15 5.0 db 1 0 0 0 0 16 4.0 db 1 0 0 0 1 17 3.0 db 1 0 0 1 0 18 2.0 db 1 0 0 1 1 19 1.0 db 1 0 1 0 0 20 0 db 1 0 1 0 1 21 1.0 db 1 0 1 1 0 22 2.0 db 1 0 1 1 1 23 3.0 db 1 1 0 0 0 24 4.0 db 1 1 0 0 1 25 5.0 db 1 1 0 1 0 26 6.0 db 1 1 0 1 1 27 7.0 db 1 1 1 0 0 28 8.0 db 1 1 1 0 1 29 9.0 db 1 1 1 1 0 30 10 db 1 1 1 1 1 31 11 db
mc13109a 22 motorola rf/if device data auxiliary register the auxiliary register contains a 3bit 1st lo capacitor selection latch and a 4bit test mode latch. operation of these latch bits are explained in figures 24, 25 and 26. figure 24. auxiliary register latch bits 4bit test mode 3bit 1st lo capacitor selection msb lsb msb lsb first local oscillator capacitor selection for 25 channel u.s. operation there is a very large frequency difference between the minimum and maximum channel frequencies in the proposed 25 channel u.s. standard. the sensitivity of the 1st lo is not large enough to accommodate this large frequency variation. fixed capacitors can be connected across the 1st lo tank circuit to change the 1st lo sensitivity. internal switches and capacitors are provided to enable microprocessor control over internal fixed capacitor values. figure 25 shows the schematic of the 1st lo tank circuit. figure 26 shows the latch control bit values. figure 25. first lo schematic lo 1 in 40 lo 1 out 41 v cap ctrl 42 internal capacitor 1st lo varactor varactor c ext l ext figure 26. 1st lo capacitor select for u.s. 25 channels 1st lo cap. bit 2 1st lo cap. bit 1 1st lo cap. bit 0 1st lo cap. select u.s. base channels u.s. handset channels varactor value over 0.5 to 2.2 v range external capacitor value external inductor value 0 0 0 0 16 25 10 6.4 pf 27 pf 0.47 m h 0 0 0 0 16 25 10 6.4 pf 33 pf 0.47 m h 0 0 1 1 1 6 10 6.4 pf 27 pf 0.47 m h 0 1 0 2 7 15 10 6.4 pf 27 pf 0.47 m h 0 1 1 3 1 6 10 6.4 pf 33 pf 0.47 m h 1 0 0 4 7 15 10 6.4 pf 33 pf 0.47 m h
mc13109a 23 motorola rf/if device data figure 27. test mode description tm # tm 3 tm 2 tm 1 tm 0 counter under test or test mode option atx v co o input signal aclk outo output expected 0 0 0 0 0 normal operation >200 mvpp 1 0 0 0 1 rx counter, upper 6 0 to 2.2 v input frequency/64 2 0 0 1 0 rx counter, lower 8 0 to 2.2 v see note below 3 0 0 1 1 rx prescaler 0 to 2.2 v input frequency/4 4 0 1 0 0 tx counter, upper 6 0 to 2.2 v input frequency/64 5 0 1 0 1 tx counter, lower 8 0 to 2.2 v see note below 6 0 1 1 0 tx prescaler >200 mvpp input frequency/4 7 0 1 1 1 reference counter 0 to 2.2 v input frequency/reference counter value 8 1 0 0 0 divide by 4, 25 0 to 2.2 v input frequency/100 9 1 0 0 1 agc gain = 10 option n/a 10 1 0 1 0 agc gain = 25 option n/a note: to determine the correct output, look at the lower 8 bits in the rx or tx register (divisor (7;0). if the value of the divisor is > 16, then the output divisor value is divisor (7;2) (the upper 6 bits of the divisor). if divisor (7;0) < 16 and divisor (3;2) > = 2, then output divisor va lue is divisor (3;2) (bits 2 and 3 of the divisor). if divisor (7;0) < 16 and divisor (3;2) < 2, then output divisor value is (divisor (3;2) + 60). test modes test mode control latch bits enable independent testing of internal counters and set agc gain options. in test mode, the atx vcoo input pin is multiplexed to the input of the counter under test and the output of the counter under test is multiplexed to the aclk outo output pin so that each counter can be individually tested. make sure test mode bits are set to a0o for normal operation. test mode operation is described in figure 27. during normal operation and when testing the tx prescaler, the atx vcoo input can be a minimum of 200 mvpp at 80 mhz and should be ac coupled. for other test modes, input signals should be standard logic levels of 0 to 2.2 v and a maximum frequency of 16 mhz. powerup defaults for control and counter registers when the ic is first powered up, all latch registers are initialized to a defined state. the mc13109a is initially placed in the rx mode with all mutes active and nothing disabled. the reference counter is set to generate a 5.0 khz reference frequency from a 10.24 mhz crystal. the mpu clock output divider is set to 10 to give the minimum clock output frequency. the tx and rx latch registers are set for usa channel frequency #21. figure 28 shows the initial powerup states for all latch registers. figure 28. latch register powerup defaults msb lsb register count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx 9965 1 0 0 1 1 0 1 1 1 0 1 1 1 0 rx 7215 0 1 1 1 0 0 0 0 1 0 1 1 1 1 ref 2048 0 0 1 0 0 0 0 0 0 0 0 0 0 0 mode n/a 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 gain n/a 1 0 1 0 0 tm n/a 0 0 0 0 0 0 0
mc13109a 24 motorola rf/if device data figure 29. i cc versus v cc at active mode figure 30. i cc versus v cc at receive mode figure 31. i cc versus v cc at standby mode figure 32. i cc versus v cc at inactive mode figure 33. rssi output versus rf in figure 34. recovered audio/thd versus f dev f dev , deviation, (khz) rf in , rf input (dbm) v cc , supply voltage (v) thd 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 v cc , supply voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 v cc , supply voltage (v) 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 v cc , supply voltage (v) 80 70 60 50 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 1.6 1.0 0.8 0.6 0.4 0.2 0 120 100 80 60 40 0 300 250 200 150 100 50 0 1.0 3.0 5.0 7.0 9.0 1.2 1.4 20 2.0 4.0 6.0 8.0 recovered audio r22 = 12 k w 6.0 5.0 4.0 3.0 2.0 1.0 0 , supply current ( a) m recovered audio (v) i cc rssi output (db) , supply current (ma) i cc , supply current (ma) i cc , supply current (ma) i cc thd (%)
mc13109a 25 motorola rf/if device data figure 35. typical expander response figure 36. typical compressor response rx audio in (dbv) 10 0 10 20 30 40 50 60 70 35 30 25 20 15 0 compressor, c in level input (dbv) 0 10 20 30 40 60 80 70 60 50 40 30 0 20 40 60 80 10 5.0 50 20 10 0 mixer 1 in (dbm) 80 70 60 50 40 30 20 10 0 0 20 40 60 80 mixer 2 in (dbm) 80 70 60 50 40 30 20 10 0 90 acl aono acl aoffo figure 37. first mixer third order intercept performance figure 38. second mixer third order intercept performance mixer output (dbm) mixer output (dbm) expander, e out (dbv) compressor level output, lim out (dbv)
mc13109a 26 motorola rf/if device data appendix a measurement of compandor attack/decay time this measurement definition is based on eia/ccitt recommendations. compressor attack time for a 12 db step up at the input, attack time is defined as the time for the output to settle to 1.5x of the final steady state value. compressor decay time for a 12 db step down at the input, decay time is defined as the time for the input to settle to 0.75x of the final steady state value. decay time 0.75x final value 1.5x final value attack time 0 mv 0 mv input output 12 db expander attack for a 6.0 db step up at the input, attack time is defined as the time for the output to settle to 0.57x of the final steady state value. expander decay for a 6.0 db step down at the input, decay time is defined as the time for the output to settle to 1.5x of the final steady state value. decay time 1.5x final value 0.57x final value attack time 0 mv input output 6.0 db 0 mv
mc13109a 27 motorola rf/if device data fb suffix plastic package case 848b04 (qfp52) issue c outline dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. detail a l 39 40 26 27 1 52 14 13 l a b v s ab m 0.20 (0.008) d s h ab 0.05 (0.002) s ab m 0.20 (0.008) d s c d b v b s ab m 0.20 (0.008) d s h ab 0.05 (0.002) s ab m 0.20 (0.008) d s c h 0.10 (0.004) c seating plane datum plane m g h e c m detail c u q x w k t r detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.22 0.38 0.009 0.015 e 2.00 2.10 0.079 0.083 f 0.22 0.33 0.009 0.013 g 0.65 bsc 0.026 bsc h 0.25 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 7.80 ref 0.307 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 0.005 u 0 0 v 12.95 13.45 0.510 0.530 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref b b detail a a, b, d jn d f base metal section bb s ab m 0.02 (0.008) d s c motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer.
mc13109a 28 motorola rf/if device data fta suffix plastic package case 93202 (thin qfp) issue d outline dimensions dim a min max min max inches 7.000 bsc 0.276 bsc millimeters a1 3.500 bsc 0.138 bsc b 7.000 bsc 0.276 bsc b1 3.500 bsc 0.138 bsc c 1.400 1.600 0.055 0.063 d 0.170 0.270 0.007 0.011 e 1.350 1.450 0.053 0.057 f 0.170 0.230 0.007 0.009 g 0.500 basic 0.020 basic h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.250 basic 0.010 basic q 1 5 1 5 r 0.150 0.250 0.006 0.010 s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref notes: 1 dimensioning and tolerancing per ansi y14.5m, 1982. 2 controlling dimension: millimeter. 3 datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4 datums t, u, and z to be determined at datum plane ab. 5 dimensions s and v to be determined at seating plane ac. 6 dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7 dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350 (0.014). 8 minimum solder plate thickness shall be 0.0076 (0.0003). 9 exact shape of each corner is optional. ???? ???? ???? a a1 t z 0.200 (0.008) ab tu u 4x z 0.200 (0.008) ac tu 4x b b1 1 12 13 24 25 36 37 48 z s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d s tu m 0.080 (0.003) z s ac section aeae ab ac ad g 0.080 (0.003) ac m top & bottom q w k x e c h 0.250 (0.010) gauge plane r 9 detail ad mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 813 54878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & canada only 18007741848 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. http://sps.motorola.com/mfax/ 85226668334 home page : http://motorola.com/sps/ mc13109a/d ?

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